1. Technical Field
This invention relates generally to electronic mobile devices, and more particularly, to a method for improved performance thereof.
2. Background Art
Recently, the capabilities and advantages of electronic mobile devices such as cellular phones and personal digital assistants (PDA's) have increased substantially. For example, increased performance has been coupled with lower cost, lower power consumption, and smaller size. It will be understood that increased performance, along with other advantages, will be constantly sought.
In a typical mobile device, such as a cellular phone, the mobile device 20 includes a mobile terminal 22 and a memory module 24 (FIG. 1). The mobile terminal 22 is capable of sending signals to the connected memory module 24, and receiving signals from the connected memory module 24. For example, the user of the device 20 may input data to the mobile terminal 22 which sends such data to the connected memory module 24 for storage therein. Also, data in the memory module 24 may be retrieved therefrom to the mobile terminal 22 for the user of the device 20. In furtherance of these objects, in the present example, the mobile terminal 22 includes an application CPU 26, a baseband CPU 28, a dynamic memory controller 30 associated with both CPUs 26, 28, a static memory controller 32 associated with both CPUs 26, 28, a plurality of pads 34 associated with the dynamic memory controller 30, and a plurality of pads 36 associated with the static memory controller 32. The pads 34 associated with the dynamic memory controller 30 contact the pads 38 of a dynamic memory 40 of the external memory module 22, while the pads 36 associated with the static memory controller 32 contact the pads 42 of a static memory 44 of the external memory module 22.
FIG. 2 illustrates a timing diagram for certain signals related to the static memory. As shown, regular clock cycles are provided by the mobile terminal 22, along with a static channel select signal, a static address control signal, an output enable or write enable signal, and a data output signal (data strings D1, D2, D3, D4 on successive rising clock signals) with latency of two clock cycles after output or write enable. (It will be understood that a number of other operational signals are included, and not illustrated for clarity). Address control bus utilization is shown (corresponding to the timing of the active, low static address control signal), as is the static data bus utilization (corresponding to the timing of data strings D1, D2, D3, D4).
FIG. 3 illustrates the timing diagram for certain signals related to the dynamic memory. Again, the regular clock signals are provided by the mobile terminal 22, along with a dynamic channel select signal, a dynamic address control signal, an SDDR (Synchronous Double Data Rate) data output signal (data strings D5, D6, D7, D8 on successive rising edges of the clock signals, with latency of two clock cycles after active, low, dynamic address control signal), and a DDR (Double Data Rate) data output signal (data strings D9, D10, D11, D12 on successive rising and falling edges of the clock signals, with latency of two clock cycles after active, low, dynamic address control signal). SDDR data bus utilization and DDR data bus utilization are also illustrated.
In a typical system, none of these operational signals (i.e., those operational signals illustrated and those operational and signals not illustrated) are multiplexed. In order to increase performance of such a device, the bus width of the mobile terminal 22 would have to be increased, as would device pin count. In addition, in this example, the active dynamic address control signal and active static address control signal occur on the same clock cycle, resulting in the necessity of using separate buses for properly carrying address control signals.
Therefore, what is needed is a method for sending data signals in a mobile device which provides a high-level of operational performance meanwhile reducing pin count and increasing bus utilization.